1. Field of Invention
The present invention relates to an embedded memory. More particularly, the present invention relates to the power source design within an embedded memory that can improve testing stability and reduce testing errors.
2. Description of Related Art
The semiconductor industry is forever striving to produce semiconductor devices that have functions superior their competitors' devices while maintaining or lowering the cost of production. Through miniaturization and sub-micron manufacturing technique, many devices can be squeezed into a very small silicon chip. Hence, cost of each device is greatly lowered. In addition, sub-micron technique is capable of forming devices with a variety of different functions within a silicon chip, thereby improving its usefulness.
Another direction in which the semiconductor industry is heading, that can improve cost of production and device functionality, is to form logic devices and memory devices together on a silicon chip. The integration of logic devices and memory devices together on a silicon chip rather than on two separate chips can reduce time delays between devices. In addition, having the logic devices and the memory devices on the same silicon chip can save production cost. This is because some of the separate processing steps necessary for fabricating logic devices and memory devices independently can be combined together.
The structure known as an embedded memory is an example of an integrated circuit (IC) that integrates dynamic random access memory (DRAM) and logic circuitry together in the same semiconductor substrate. The embedded DRAM memory is capable of accessing large quantities of data in a very short time, and hence has many useful applications. For example, microprocessors and digital signal processors are some of the integrated circuits that use embedded memory.
FIG. 1 is a diagram showing the structure of a conventional embedded memory. An embedded memory 10 includes a DRAM 12, a logic unit 14 and a testing mode circuit with input/output ports 16. The DRAM 12, the logic unit 14 and the testing mode circuit with input/output ports 16 all use the same power source Vcc to supply voltage necessary for carrying out various internal functions of the embedded memory 10. However, when the DRAM 12 is undergoing a testing operation, the logic unit 14 may generate direct current internally due to a floating node if the DRAM 12 and the logic unit 14 share the same power source Vcc. Consequently, the testing environment and conditions of the DRAM may be affected leading to testing instability and errors. In addition, the actual amount of current drained by the DRAM or the occurrence of any out-of-range parameters may be difficult to track.
In light of the foregoing, there is a need to provide an improved power source design for the embedded memory.